| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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Leveraging FDSOI through body bias domain partitioning and bias search Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel |
Leveraging FDSOI through body bias domain partitioning and bias search Details |
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Invited - Wireless sensor nodes for environmental monitoring in internet of things Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Daniel Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh |
Invited - Wireless sensor nodes for environmental monitoring in internet of things Details |
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Nonvolatile memory design based on ferroelectric FETs Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif I. Khan, Sayeef S. Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan |
Nonvolatile memory design based on ferroelectric FETs Details |
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Reducing serial I/O power in error-tolerant applications by efficient lossy encoding Phillip Stanley-Marbell, Martin C. Rinard |
Reducing serial I/O power in error-tolerant applications by efficient lossy encoding Details |
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Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory Tseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, Shuo-Han Chen |
Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory Details |
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Perform-ML: performance optimized machine learning by platform and content aware customization Azalia Mirhoseini, Bita Darvish Rouhani, Ebrahim M. Songhori, Farinaz Koushanfar |
Perform-ML: performance optimized machine learning by platform and content aware customization Details |
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Designing approximate circuits using clock overgating Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
Designing approximate circuits using clock overgating Details |
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Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems? Geoff V. Merrett |
Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems? Details |
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An expected hypervolume improvement algorithm for architectural exploration of embedded processors Hongwei Wang, Jinglin Shi, Ziyuan Zhu |
An expected hypervolume improvement algorithm for architectural exploration of embedded processors Details |
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Miao Hu, John Paul Strachan, Zhiyong Li, Emmanuelle M. Grafals, Noraica Davila, Catherine Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, R. Stanley Williams |
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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi |
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks Details |
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Chung-Wei Lin, Huafeng Yu |
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Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan |
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Invited - Heterogeneous datacenters: options and opportunities Jason Cong, Muhuan Huang, Di Wu, Cody Hao Yu |
Invited - Heterogeneous datacenters: options and opportunities Details |
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A low-cost conflict-free NoC for GPGPUs Xia Zhao, Sheng Ma, Yuxi Liu, Lieven Eeckhout, Zhiying Wang |
A low-cost conflict-free NoC for GPGPUs Details |
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A Monte Carlo simulation flow for SEU analysis of sequential circuits Meng Li, Ye Wang, Michael Orshansky |
A Monte Carlo simulation flow for SEU analysis of sequential circuits Details |
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A high-resolution side-channel attack on last-level cache Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel |
A high-resolution side-channel attack on last-level cache Details |
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SecDCP: secure dynamic cache partitioning for efficient timing channel protection Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh |
SecDCP: secure dynamic cache partitioning for efficient timing channel protection Details |
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Privacy preserving localization for smart automotive systems Siam U. Hussain, Farinaz Koushanfar |
Privacy preserving localization for smart automotive systems Details |
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ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading Florian Kriebel, Semeen Rehman, Muhammad Shafique, Jörg Henkel |
ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading Details |
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Zhuo Feng |
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Precise error determination of approximated components in sequential circuits with model checking Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler |
Precise error determination of approximated components in sequential circuits with model checking Details |
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Design partitioning for large-scale equivalence checking and functional correction Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang |
Design partitioning for large-scale equivalence checking and functional correction Details |
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Legalization algorithm for multiple-row height standard cell design Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young |
Legalization algorithm for multiple-row height standard cell design Details |
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Lower power by voltage stacking: a fine-grained system design approach Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez |
Lower power by voltage stacking: a fine-grained system design approach Details |
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Designing guardbands for instantaneous aging effects Victor M. van Santen, Hussam Amrouch, Javier Martín-Martínez, Montserrat Nafría, Jörg Henkel |
Designing guardbands for instantaneous aging effects Details |
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SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy |
SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost Details |
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AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark Tehranipoor |
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs Details |
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An area-efficient consolidated configurable error correction for approximate hardware accelerators Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique, Jörg Henkel |
An area-efficient consolidated configurable error correction for approximate hardware accelerators Details |
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Hybrid STT-CMOS designs for reverse-engineering prevention Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Kris Gaj, Houman Homayoun |
Hybrid STT-CMOS designs for reverse-engineering prevention Details |
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James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden |
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Simplifying deep neural networks for neuromorphic architectures Jaeyong Chung, Taehwan Shin |
Simplifying deep neural networks for neuromorphic architectures Details |
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Efficient transistor-level timing yield estimation via line sampling Hiromitsu Awano, Takashi Sato |
Efficient transistor-level timing yield estimation via line sampling Details |
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Synergistic timing speculation for multi-threaded programs Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty |
Synergistic timing speculation for multi-threaded programs Details |
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Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco |
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification Details |
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Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen |
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation Details |
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Invited - The case for embedded scalable platforms Luca P. Carloni |
Invited - The case for embedded scalable platforms Details |
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Notifying memories: a case-study on data-flow applications with NoC interfaces implementation Kevin J. M. Martin, Mostafa Rizk, Martha Johanna Sepúlveda, Jean-Philippe Diguet |
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation Details |
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An efficient method for multi-level approximate logic synthesis under error rate constraint Yi Wu, Weikang Qian |
An efficient method for multi-level approximate logic synthesis under error rate constraint Details |
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Invited - Ultra low power integrated transceivers for near-field IoT Mihai Sanduleanu, Ibrahim Abe M. Elfadel |
Invited - Ultra low power integrated transceivers for near-field IoT Details |
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Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge |
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM Details |
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Resource budgeting for reliability in reconfigurable architectures Hongyan Zhang, Lars Bauer, Jörg Henkel |
Resource budgeting for reliability in reconfigurable architectures Details |
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Improving high-level synthesis with decoupled data structure optimization Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang |
Improving high-level synthesis with decoupled data structure optimization Details |
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Wei Wen, Chunpeng Wu, Yandan Wang, Kent W. Nixon, Qing Wu, Mark Barnell, Hai Li, Yiran Chen |
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Predicting electromigration mortality under temperature and product lifetime specifications Vivek Mishra, Sachin S. Sapatnekar |
Predicting electromigration mortality under temperature and product lifetime specifications Details |
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Real-time co-scheduling of multiple dataflow graphs on multi-processor systems Shin-Haeng Kang, Duseok Kang, Hoeseok Yang, Soonhoi Ha |
Real-time co-scheduling of multiple dataflow graphs on multi-processor systems Details |
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Information dispersion for trojan defense through high-level synthesis S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong |
Information dispersion for trojan defense through high-level synthesis Details |
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MTJ variation monitor-assisted adaptive MRAM write Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta |
MTJ variation monitor-assisted adaptive MRAM write Details |
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Optimal design of JPEG hardware under the approximate computing paradigm Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar |
Optimal design of JPEG hardware under the approximate computing paradigm Details |
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Similarity-based wakeup management for mobile systems in connected standby Chun-Hao Kao, Sheng-Wei Cheng, Pi-Cheng Hsiu |
Similarity-based wakeup management for mobile systems in connected standby Details |
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Re-target-able software power management framework using SoC data auto-generation Piyali Goswami, Sushaanth Srirangapathi, Chetan Matad, Stanley Liu |
Re-target-able software power management framework using SoC data auto-generation Details |
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Grace Li Zhang, Bing Li, Ulf Schlichtmann |
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Catching the flu: emerging threats from a third party power management unit Rajesh Jayashankara Shridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy |
Catching the flu: emerging threats from a third party power management unit Details |
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PLL to the rescue: a novel EM fault countermeasure Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger |
PLL to the rescue: a novel EM fault countermeasure Details |
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The cat and mouse in split manufacturing Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran |
The cat and mouse in split manufacturing Details |
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Statistical path tracing in timing graphs Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya |
Statistical path tracing in timing graphs Details |
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Remote attestation for low-end embedded devices: the prover's perspective Franz Ferdinand Brasser, Kasper Bonne Rasmussen, Ahmad-Reza Sadeghi, Gene Tsudik |
Remote attestation for low-end embedded devices: the prover's perspective Details |
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A framework for verification of SystemC TLM programs with model slicing: a case study Reza Hajisheykhi, Mohammad Roohitavaf, Ali Ebnenasir, Sandeep S. Kulkarni |
A framework for verification of SystemC TLM programs with model slicing: a case study Details |
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NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen |
NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation Details |
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Yang Song, Kambiz Samadi, Bill Lin |
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Reliability-aware design to suppress aging Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel |
Reliability-aware design to suppress aging Details |
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A novel time and voltage based SAR ADC design with self-learning technique Abhilash Karnatakam Nagabhushana, Haibo Wang |
A novel time and voltage based SAR ADC design with self-learning technique Details |
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Matthew Poremba, Tao Zhang, Yuan Xie |
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Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang |
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture Details |
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Match-making for monolithic 3D IC: finding the right technology node Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
Match-making for monolithic 3D IC: finding the right technology node Details |
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Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang |
Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning Details |
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Practical statistical static timing analysis with current source models Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala |
Practical statistical static timing analysis with current source models Details |
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A low-power dynamic divider for approximate applications Soheil Hashemi, R. Iris Bahar, Sherief Reda |
A low-power dynamic divider for approximate applications Details |
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Fault injection acceleration by simultaneous injection of non-interacting faults Mojtaba Ebrahimi, Mohammad Hadi Moshrefpour, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori |
Fault injection acceleration by simultaneous injection of non-interacting faults Details |
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Honghuang Lin, Peng Li |
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Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino |
Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals Details |
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Li Du, Chun-Chen Liu, Adrian Tang, Yan Zhang, Yilei Li, Kye Cheung, Mau-Chung Frank Chang |
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Invited - Specification and modeling for systems-on-chip security verification Sharad Malik, Pramod Subramanyan |
Invited - Specification and modeling for systems-on-chip security verification Details |
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Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo |
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I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang |
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Invited - Who is the major threat to tomorrow's security?: you, the hardware designer Wayne P. Burleson, Onur Mutlu, Mohit Tiwari |
Invited - Who is the major threat to tomorrow's security?: you, the hardware designer Details |
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Comprehensive optimization of scan chain timing during late-stage IC implementation Kun Young Chung, Andrew B. Kahng, Jiajia Li |
Comprehensive optimization of scan chain timing during late-stage IC implementation Details |
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nZDC: a compiler technique for near zero silent data corruption Moslem Didehban, Aviral Shrivastava |
nZDC: a compiler technique for near zero silent data corruption Details |
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Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar |
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AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache Xunchao Chen, Navid Khoshavi, Jian Zhou, Dan Huang, Ronald F. DeMara, Jun Wang, Wujie Wen, Yiran Chen |
AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache Details |
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Timing-driven cell placement optimization for early slack histogram compression Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo |
Timing-driven cell placement optimization for early slack histogram compression Details |
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BLESS: a simple and efficient scheme for prolonging PCM lifetime Marjan Asadinia, Majid Jalili, Hamid Sarbazi-Azad |
BLESS: a simple and efficient scheme for prolonging PCM lifetime Details |
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A fast simulator for the analysis of sub-threshold thermal noise transients Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky |
A fast simulator for the analysis of sub-threshold thermal noise transients Details |
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Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis Florin Burcea, Husni M. Habal, Helmut E. Graeb |
Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis Details |
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Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi |
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Minimum-implant-area-aware detailed placement with spacing constraints Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu |
Minimum-implant-area-aware detailed placement with spacing constraints Details |
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A distributed timing analysis framework for large designs Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran |
A distributed timing analysis framework for large designs Details |
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Flip-flop clustering by weighted K-means algorithm Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu |
Flip-flop clustering by weighted K-means algorithm Details |
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Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li |
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Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu |
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Alireza Shafaei, Hassan Afzali-Kusha, Massoud Pedram |
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Columba: co-layout synthesis for continuous-flow microfluidic biochips Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann |
Columba: co-layout synthesis for continuous-flow microfluidic biochips Details |
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DAG-aware logic synthesis of datapaths Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan |
DAG-aware logic synthesis of datapaths Details |
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Switched by input: power efficient structure for RRAM-based convolutional neural network Lixue Xia, Tianqi Tang, Wenqin Huangfu, Ming Cheng, Xiling Yin, Boxun Li, Yu Wang, Huazhong Yang |
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Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann |
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Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra |
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Statistical fault injection for impact-evaluation of timing errors on application performance Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis |
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Yong Shim, Abhronil Sengupta, Kaushik Roy |
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Accelerating soft-error-rate (SER) estimation in the presence of single event transients Ji Li, Jeffrey Draper |
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Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems Wen-Hung Huang, Jian-Jia Chen |
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Physics-based full-chip TDDB assessment for BEOL interconnects Xin Huang, Valeriy Sukharev, Zhongdong Qi, Taeyoung Kim, Sheldon X.-D. Tan |
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An MIG-based compiler for programmable logic-in-memory architectures Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli |
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Redundant via insertion for multiple-patterning directed-self-assembly lithography Seongbo Shim, Woohyun Chung, Youngsoo Shin |
Redundant via insertion for multiple-patterning directed-self-assembly lithography Details |
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Vincent Camus, Jeremy Schlachter, Christian C. Enz |
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Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age Amin Rezaei, Danella Zhao, Masoud Daneshtalab, Hongyi Wu |
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Optimal and fast throughput evaluation of CSDF Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin |
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Exploiting design-for-debug for flexible SoC security architecture Abhishek Basak, Swarup Bhunia, Sandip Ray |
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Achieving lightweight multicast in asynchronous networks-on-chip using local speculation Kshitij Bhardwaj, Steven M. Nowick |
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TEMP: thread batch enabled memory partitioning for GPU Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li |
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MORPh: mobile OLED-friendly recording and playback system for low power video streaming Xiang Chen, Jiachen Mao, Jiafei Gao, Kent W. Nixon, Yiran Chen |
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Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw |
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Distributed scheduling for many-cores using cooperative game theory Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel |
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Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smaïl Niar |
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Invited - Can IoT be secured: emerging challenges in connecting the unconnected Nancy Cam-Winget, Ahmad-Reza Sadeghi, Yier Jin |
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Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei |
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Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy |
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SECRET: smartly EnCRypted energy efficient non-volatile memories Shivam Swami, Joydeep Rakshit, Kartik Mohanram |
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A novel cross-layer framework for early-stage power delivery and architecture co-exploration Cheng Zhuo, Kassan Unda, Yiyu Shi, Wei-Kai Shih |
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High-level synthesis for micro-electrode-dot-array digital microfluidic biochips Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee |
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DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li |
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Zewei Li, Yongpan Liu, Daming Zhang, Chun Jason Xue, Zhangyuan Wang, Xin Shi, Wenyu Sun, Jiwu Shu, Huazhong Yang |
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PDS: pseudo-differential sensing scheme for STT-MRAM Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao |
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Practical public PUF enabled by solving max-flow problem on chip Meng Li, Jin Miao, Kai Zhong, David Z. Pan |
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Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha |
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Incremental layer assignment for critical path timing Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan |
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A semantics-aware design for mounting remote sensors on mobile systems Yu-Wen Jong, Pi-Cheng Hsiu, Sheng-Wei Cheng, Tei-Wei Kuo |
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Improving performance and lifetime of NAND storage systems using relaxed program sequence Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong Kim |
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Efficient design space exploration via statistical sampling and AdaBoost learning Dandan Li, Shuzhen Yao, Yu-Hang Liu, Senzhang Wang, Xian-He Sun |
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Mathias Soeken, Anupam Chattopadhyay |
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Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT Payam Heydari |
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Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak |
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Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li |
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A quantum annealing approach for boolean satisfiability problem Juexiao Su, Tianheng Tu, Lei He |
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Invited - Cross-layer approaches for soft error modeling and mitigation Mojtaba Ebrahimi, Mehdi Baradaran Tahoori |
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GarbledCPU: a MIPS processor for secure computation in hardware Ebrahim M. Songhori, Shaza Zeitouni, Ghada Dessouky, Thomas Schneider, Ahmad-Reza Sadeghi, Farinaz Koushanfar |
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Xin Zhan, Peng Li, Edgar Sánchez-Sinencio |
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Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich |
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Accurate phase-level cross-platform power and performance estimation Xinnian Zheng, Lizy K. John, Andreas Gerstlauer |
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A model-driven approach to warp/thread-block level GPU cache bypassing Hongwen Dai, Chao Li, Huiyang Zhou, Saurabh Gupta, Christos Kartsaklis, Mike Mantor |
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Invited - Cross-layer approximate computing: from logic to architectures Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel |
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Area optimization of resilient designs guided by a mixed integer geometric program Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel |
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Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li |
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A probabilistic scheduling framework for mixed-criticality systems Alejandro Masrur |
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A quantitative analysis on microarchitectures of modern CPU-FPGA platforms Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei |
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Random modulo: a new processor cache design for real-time critical systems Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla |
Random modulo: a new processor cache design for real-time critical systems Details |
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This invention is integrated on a RTL implementation of an enhanced Cobham Gaisler LEON3 processor. The full bitstream, where this invention is integrated in all first level data and instruction caches can be requested to Cobham Gaisler as announced in their website: http://www.gaisler.com/index.php/products/processors/leon3
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Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
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Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie |
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Energy efficient computation with asynchronous races Advait Madhavan, Timothy Sherwood, Dmitri B. Strukov |
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Fa Wang, Xin Li |
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Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity Dean Sullivan, Orlando Arias, Lucas Davi, Per Larsen, Ahmad-Reza Sadeghi, Yier Jin |
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Hehe Li, Yongpan Liu, Chenchen Fu, Chun Jason Xue, Donglai Xiang, Jinshan Yue, Jinyang Li, Daming Zhang, Jingtong Hu, Huazhong Yang |
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MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources Wen-Hung Huang, Jian-Jia Chen, Jan Reineke |
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DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li |
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StitchUp: automatic control flow protection for high level synthesis circuits Shane T. Fleming, David B. Thomas |
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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Kenneth L. Shepard, Luca P. Carloni |
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Seyed Ali Rokni, Hassan Ghasemzadeh |
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A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler |
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Invited - Cross-layer modeling and optimization for electromigration induced reliability Taeyoung Kim, Zeyu Sun, Chase Cook, Hengyang Zhao, Ruiwen Li, Daniel Wong, Sheldon X.-D. Tan |
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Multiple patterning layout decomposition considering complex coloring rules Hua-Yu Chang, Iris Hui-Ru Jiang |
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Matthew Vilim, Henry Duwe, Rakesh Kumar |
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Invited - Towards fail-operational ethernet based in-vehicle networks Mischa Möstl, Daniel Thiele, Rolf Ernst |
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Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn |
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On harmonic fixed-priority scheduling of periodic real-time tasks with constrained deadlines Tianyi Wang, Qiushi Han, Shi Sha, Wujie Wen, Gang Quan, Meikang Qiu |
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Chun-Chen Liu, Yen-Hsiang Wang, Yilei Li, Chien-Heng Wong, Tien Pei Chou, Young-Kai Chen, M.-C. Frank Chang |
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An MPSoC for energy-efficient database query processing Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis |
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Physical unclonable functions-based linear encryption against code reuse attacks Pengfei Qiu, Yongqiang Lyu, Jiliang Zhang, Xingwei Wang, Di Zhai, Dongsheng Wang, Gang Qu |
Physical unclonable functions-based linear encryption against code reuse attacks Details |
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Invited - Things, trouble, trust: on building trust in IoT systems Tigist Abera, N. Asokan, Lucas Davi, Farinaz Koushanfar, Andrew Paverd, Ahmad-Reza Sadeghi, Gene Tsudik |
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Invited - A box of dots: using scan-based path delay test for timing verification Alfred L. Crouch, John C. Potter |
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Hadi Asghari Moghaddam, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim |
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Write-back aware shared last-level cache management for hybrid main memory Deshan Zhang, Lei Ju, Mengying Zhao, Xiang Gao, Zhiping Jia |
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Invited - Context-aware energy-efficient communication for IoT sensor nodes Shreyas Sen |
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Integration of multi-sensor occupancy grids into automotive ECUs Tiana A. Rakotovao, Julien Mottin, Diego Puschini, Christian Laugier |
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Improving mobile gaming performance through cooperative CPU-GPU thermal management Alok Prakash, Hussam Amrouch, Muhammad Shafique, Tulika Mitra, Jörg Henkel |
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Architecting energy-efficient STT-RAM based register file on GPGPUs via delta compression Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu |
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