| Title: |
Efficient transistor-level timing yield estimation via line sampling |
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| Authors: |
Hiromitsu Awano |
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Kyoto University Yoshida-honmachi, Sakyo, Kyoto, Japan, 606–8501, Graduate School of Informatics
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| Takashi Sato |
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Kyoto University Yoshida-honmachi, Sakyo, Kyoto, Japan, 606–8501, Graduate School of Informatics
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| DBLP Key: |
conf/dac/AwanoS16
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