| Title: |
Random modulo: a new processor cache design for real-time critical systems |
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| Authors: |
Carles Hernández |
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Barcelona Supercomputing Center (BSC), Barcelona (Spain)
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| Jaume Abella |
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Barcelona Supercomputing Center (BSC), Barcelona (Spain)
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| Andrea Gianarro |
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Cobham Gaisler, Gothenburg (Sweden)
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| Jan Andersson |
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Cobham Gaisler, Gothenburg (Sweden)
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| Francisco J. Cazorla |
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Barcelona Supercomputing Center (BSC), Barcelona (Spain)
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| Sharing: |
Other
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| Verification: |
Authors have
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| Artifact Evaluation Badge: |
none
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| DBLP Key: |
conf/dac/HernandezAGAC16
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| Author Comments: |
This invention is integrated on a RTL implementation of an enhanced Cobham Gaisler LEON3 processor. The full bitstream, where this invention is integrated in all first level data and instruction caches can be requested to Cobham Gaisler as announced in their website: http://www.gaisler.com/index.php/products/processors/leon3 |