Design Automation Conference, DAC 2016


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Title: An efficient method for multi-level approximate logic synthesis under error rate constraint
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Authors: Yi Wu
  • Shanghai Jiao Tong University, University of Michigan-Shanghai Jiao Tong University Joint Institute
Weikang Qian
  • Shanghai Jiao Tong University, University of Michigan-Shanghai Jiao Tong University Joint Institute
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DBLP Key: conf/dac/WuQ16
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