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Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution
André Inácio Reis
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Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution
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Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid
Sheng-En David Lin, Dae Hyun Kim
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Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid
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Machine Learning for Feature-Based Analytics
Li-C. Wang
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Machine Learning for Feature-Based Analytics
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Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout
Andrew B. Kahng
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Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout
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ISPD 2018 Initial Detailed Routing Contest and Benchmarks
Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu
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ISPD 2018 Initial Detailed Routing Contest and Benchmarks
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Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits
Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos
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Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits
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Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design
Anthony M. Hill
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Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design
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Interconnect Physical Optimization
K. Charles Janac
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Interconnect Physical Optimization
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Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, Yoon Kah Leow
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Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
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Power Grid Reduction by Sparse Convex Optimization
Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan
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Power Grid Reduction by Sparse Convex Optimization
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Theory and Algorithms of Physical Design
Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng
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Theory and Algorithms of Physical Design
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On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques
Alexey Lvov, Gustavo E. Téllez, Gi-Joon Nam
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On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques
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Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications
Elliott Delaye, Ashish Sirasao, Ehsan Ghasemi
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Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications
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Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework
S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson
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Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework
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Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics
Andrew B. Kahng, Christopher Moyes, Sriram Venkatesh, Lutong Wang
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Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics
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The Pressing Need for Electromigration-Aware Physical Design
Jens Lienig, Matthias Thiele
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The Pressing Need for Electromigration-Aware Physical Design
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Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting
Biying Xu, Bulent Basaran, Ming Su, David Z. Pan
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Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting
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Pioneer Research on Mathematical Models and Methods for Physical Design
Chris Chu
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Pioneer Research on Mathematical Models and Methods for Physical Design
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Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
Bon Woong Ku, Kyungwook Chang, Sung Kyu Lim
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Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
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Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees
Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
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Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees
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Concurrent High Performance Processor Design: From Logic to PD in Parallel
Leon Stok
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Concurrent High Performance Processor Design: From Logic to PD in Parallel
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Tree Structures and Algorithms for Physical Design
Chung-Kuan Cheng, Ronald L. Graham, Ilgweon Kang, Dongwon Park, Xinyuan Wang
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Tree Structures and Algorithms for Physical Design
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Challenges in Large FPGA-based Logic Emulation Systems
William N. N. Hung, Richard Sun
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Challenges in Large FPGA-based Logic Emulation Systems
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Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning
Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan
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Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning
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Machine Learning Applications in Physical Design: Recent Results and Directions
Andrew B. Kahng
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Machine Learning Applications in Physical Design: Recent Results and Directions
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Interconnect Optimization Considering Multiple Critical Paths
Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam
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Interconnect Optimization Considering Multiple Critical Paths
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Flexibility: FPGAs and CAD in Deep Learning Acceleration
Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
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Flexibility: FPGAs and CAD in Deep Learning Acceleration
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