| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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LogCA: A High-Level Performance Model for Hardware Accelerators Muhammad Shoaib Bin Altaf, David A. Wood |
LogCA: A High-Level Performance Model for Hardware Accelerators Details |
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Clank: Architectural Support for Intermittent Computation Matthew Hicks |
Clank: Architectural Support for Intermittent Computation Details |
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Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas |
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Doowon Lee, Valeria Bertacco |
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Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures Zhaoxia Deng, Ariel Feldman, Stuart A. Kurtz, Frederic T. Chong |
Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures Details |
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Accelerating GPU Hardware Transactional Memory with Snapshot Isolation Sui Chen, Lu Peng, Samuel Irving |
Accelerating GPU Hardware Transactional Memory with Snapshot Isolation Details |
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There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh |
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes Details |
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SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally |
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks Details |
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A Programmable Galois Field Processor for the Internet of Things Yajing Chen, Shengshuo Lu, Cheng Fu, David T. Blaauw, Ronald Dreslinski Jr., Trevor N. Mudge, Hun-Seok Kim |
A Programmable Galois Field Processor for the Internet of Things Details |
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Hiding the Long Latency of Persist Barriers Using Speculative Execution Seunghee Shin, James Tuck, Yan Solihin |
Hiding the Long Latency of Persist Barriers Using Speculative Execution Details |
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Redundant Memory Array Architecture for Efficient Selective Protection Ruohuang Zheng, Michael C. Huang |
Redundant Memory Array Architecture for Efficient Selective Protection Details |
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Decoupled Affine Computation for SIMT GPUs Kai Wang, Calvin Lin |
Decoupled Affine Computation for SIMT GPUs Details |
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ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories Amro Awad, Yipeng Wang, Deborah Shands, Yan Solihin |
ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories Details |
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Mario Drumond, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi, Boris Grot, Dionisios N. Pnevmatikatos |
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Bespoke Processors for Applications with Ultra-low Area and Power Constraints Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori |
Bespoke Processors for Applications with Ultra-low Area and Power Constraints Details |
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Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM Rajat Kateja, Anirudh Badam, Sriram Govindan, Bikash Sharma, Greg Ganger |
Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM Details |
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ShortCut: Architectural Support for Fast Object Access in Scripting Languages Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas |
ShortCut: Architectural Support for Fast Object Access in Scripting Languages Details |
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Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent Christopher De Sa, Matthew Feldman, Christopher Ré, Kunle Olukotun |
Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent Details |
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CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures Gokul Subramanian Ravi, Mikko H. Lipasti |
CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures Details |
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Access Pattern-Aware Cache Management for Improving Data Utilization in GPU Gunjae Koo, Yunho Oh, Won Woo Ro, Murali Annavaram |
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU Details |
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Do-It-Yourself Virtual Memory Translation Hanna Alam, Tianhao Zhang, Mattan Erez, Yoav Etsion |
Do-It-Yourself Virtual Memory Translation Details |
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APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures Rahul Boyapati, Jiayi Huang, Pritam Majumder, Ki Hwan Yum, Eun Jung Kim |
APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures Details |
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Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB Jee Ho Ryoo, Nagendra Gulur, Shuang Song, Lizy K. John |
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB Details |
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Jenga: Software-Defined Cache Hierarchies Po-An Tsai, Nathan Beckmann, Daniel Sánchez |
Jenga: Software-Defined Cache Hierarchies Details |
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Hailong Yang, Quan Chen, Moeiz Riaz, Zhongzhi Luan, Lingjia Tang, Jason Mars |
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MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability Akhil Arunkumar, Evgeny Bolotin, Benjamin Cho, Ugljesa Milic, Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu, David W. Nellans |
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability Details |
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Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio González |
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Hardware Translation Coherence for Virtualized Systems Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee |
Hardware Translation Coherence for Virtualized Systems Details |
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ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan |
ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks Details |
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Tony Nowatzki, Vinay Gangadhar, Newsha Ardalani, Karthikeyan Sankaralingam |
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Maximizing CNN Accelerator Efficiency Through Resource Partitioning Yongming Shen, Michael Ferdman, Peter Milder |
Maximizing CNN Accelerator Efficiency Through Resource Partitioning Details |
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Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism Jiecao Yu, Andrew Lukefahr, David J. Palframan, Ganesh S. Dasika, Reetuparna Das, Scott A. Mahlke |
Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism Details |
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ThermoGater: Thermally-Aware On-Chip Voltage Regulation S. Karen Khatamifard, Longfei Wang, Weize Yu, Selçuk Köse, Ulya R. Karpuzcu |
ThermoGater: Thermally-Aware On-Chip Voltage Regulation Details |
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Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves Ofir Weisse, Valeria Bertacco, Todd M. Austin |
Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves Details |
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Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems Matthew D. Sinclair, Johnathan Alsop, Sarita V. Adve |
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems Details |
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Non-Speculative Load-Load Reordering in TSO Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras |
Non-Speculative Load-Load Reordering in TSO Details |
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Minesh Patel, Jeremie S. Kim, Onur Mutlu |
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Quality of Service Support for Fine-Grained Sharing on GPUs Zhenning Wang, Jun Yang, Rami G. Melhem, Bruce R. Childers, Youtao Zhang, Minyi Guo |
Quality of Service Support for Fine-Grained Sharing on GPUs Details |
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Plasticine: A Reconfigurable Architecture For Parallel Paterns Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matthew Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun |
Plasticine: A Reconfigurable Architecture For Parallel Paterns Details |
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Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez |
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism Details |
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HeteroOS: OS Design for Heterogeneous Memory Management in Datacenter Sudarsun Kannan, Ada Gavrilovska, Vishal Gupta, Karsten Schwan |
HeteroOS: OS Design for Heterogeneous Memory Management in Datacenter Details |
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Architectural Support for Server-Side PHP Processing Dibakar Gope, David J. Schlais, Mikko H. Lipasti |
Architectural Support for Server-Side PHP Processing Details |
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In-Datacenter Performance Analysis of a Tensor Processing Unit Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon |
In-Datacenter Performance Analysis of a Tensor Processing Unit Details |
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Footprint: Regulating Routing Adaptiveness in Networks-on-Chip Binzhang Fu, John Kim |
Footprint: Regulating Routing Adaptiveness in Networks-on-Chip Details |
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A Programmable Hardware Accelerator for Simulating Dynamical Systems Jaeha Kung, Yun Long, Duckhwan Kim, Saibal Mukhopadhyay |
A Programmable Hardware Accelerator for Simulating Dynamical Systems Details |
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InvisiMem: Smart Memory Defenses for Memory Bus Side Channel Shaizeen Aga, Satish Narayanasamy |
InvisiMem: Smart Memory Defenses for Memory Bus Side Channel Details |
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EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks Masoumeh Ebrahimi, Masoud Daneshtalab |
EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks Details |
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Arun Subramaniyan, Reetuparna Das |
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Chang Hyun Park, Taekyung Heo, Jungi Jeong, Jaehyuk Huh |
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EDDIE: EM-Based Detection of Deviations in Program Execution Alireza Nazari, Nader Sehatbakhsh, Monjur Alam, Alenka G. Zajic, Milos Prvulovic |
EDDIE: EM-Based Detection of Deviations in Program Execution Details |
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DICE: Compressing DRAM Caches for Bandwidth and Capacity Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi |
DICE: Compressing DRAM Caches for Bandwidth and Capacity Details |
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Aasheesh Kolli, Vaibhav Gogte, Ali G. Saidi, Stephan Diestelhorst, Peter M. Chen, Satish Narayanasamy, Thomas F. Wenisch |
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XPro: A Cross-End Processing Architecture for Data Analytics in Wearables Aosen Wang, Lizhong Chen, Wenyao Xu |
XPro: A Cross-End Processing Architecture for Data Analytics in Wearables Details |
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Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei |
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware Details |
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