ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2016


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Title: Brief Announcement: MIC++: Accelerating Maximal Information Coefficient Calculation with GPUs and FPGAs
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Authors: Chao Wang
  • University of Science and Technology of China, Hefei, China, School of Computer Science
  • University of Science and Technology of China, Suzhou, China, School of Software Engineering
Xi Li
  • University of Science and Technology of China, Hefei, China, School of Computer Science
  • University of Science and Technology of China, Suzhou, China, School of Software Engineering
Aili Wang
  • University of Science and Technology of China, Hefei, China, School of Computer Science
  • University of Science and Technology of China, Suzhou, China, School of Software Engineering
Xuehai Zhou
  • University of Science and Technology of China, Hefei, China, School of Computer Science
  • University of Science and Technology of China, Suzhou, China, School of Software Engineering
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DBLP Key: conf/spaa/WangLWZ16
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