DCA: a DRAM-cache-aware DRAM controller

Article Details
Title:	DCA: a DRAM-cache-aware DRAM controller
Article URLs:	https://doi.org/10.1109/SC.2016.75 http://doi.ieeecomputersociety.org/10.1109/SC.2016.75 http://dl.acm.org/citation.cfm?id=3015006
Alternative Article URLs:
Authors:	Cheng-Chieh Huang	University of Edinburgh, Institute of Computing Systems Architecture
	Vijay Nagarajan	University of Edinburgh, Institute of Computing Systems Architecture
	Arpit Joshi	University of Edinburgh, Institute of Computing Systems Architecture
Sharing:	Unknown
Verification:	Authors have not verified information
Artifact Evaluation Badge:	none
Artifact URLs:
Artifact Correspondence Email Addresses:
NSF Award Numbers:
DBLP Key:	conf/sc/HuangNJ16
Author Comments:

ACM/IEEE Intl. Conf. for High Perf. Computing, Networking, Storage and Analysis, SC 2016