Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core

Article Details
Title:	Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
Article URLs:	https://doi.org/10.1109/RTSS.2018.00060 http://doi.ieeecomputersociety.org/10.1109/RTSS.2018.00060
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Authors:	Sebastian Hahn	Saarland University, Saarland Informatics Campus
Authors:	Jan Reineke	Saarland University, Saarland Informatics Campus
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DBLP Key:	conf/rtss/0001R18
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IEEE Real-Time Systems Symposium, RTSS 2018