Hierarchical Reversible Logic Synthesis Using LUTs

Article Details
Title:	Hierarchical Reversible Logic Synthesis Using LUTs
Article URLs:	https://doi.org/10.1145/3061639.3062261
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Authors:	Mathias Soeken	EPFL, Integrated Systems Laboratory
	Martin Roetteler	Microsoft Research
	Nathan Wiebe	Microsoft Research
	Giovanni De Micheli	EPFL, Integrated Systems Laboratory
Sharing:	Unknown
Verification:	Authors have not verified information
Artifact Evaluation Badge:	none
Artifact URLs:	https://github.com/msoeken/cirkit
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NSF Award Numbers:
DBLP Key:	conf/dac/SoekenRWM17
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Design Automation Conference, DAC 2017