POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support

Article Details
Title:	POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
Article URLs:	https://doi.org/10.1145/2967938.2974051 http://ieeexplore.ieee.org/document/7756777/
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Authors:	Florian Haas	University of Augsburg, Department of Computer Science
	Sebastian Weis	University of Augsburg, Department of Computer Science
	Theo Ungerer	University of Augsburg, Department of Computer Science
	Gilles Pokam	Intel Corporation
	Youfeng Wu	Intel Corporation
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DBLP Key:	conf/IEEEpact/HaasWUPW16
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IEEE/ACM Intl. Conf. on Parallel Architectures and Compilation Techniques, PACT 2016