| Title: |
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs |
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| Authors: |
Nitin Chugh |
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International Institute of Information Technology
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| Vinay Vasista |
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Indian Institute of Science, Dept of CSA
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| Suresh Purini |
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International Institute of Information Technology
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| Uday Bondhugula |
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Indian Institute of Science, Dept of CSA
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| Sharing: |
Unknown
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| Verification: |
Authors have
not verified
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| Artifact Evaluation Badge: |
none
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| DBLP Key: |
conf/IEEEpact/ChughVPB16
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| Author Comments: |
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